1. Field of the Invention
The present invention relates to a semiconductor device featuring an overlay mark used in a photolithography process for forming a multi-layered wiring structure on a substrate.
2. Description of the Related Art
In a method for manufacturing a semiconductor device, a semiconductor substrate such as a monocrystalline silicon substrate (wafer) is prepared, and various semiconductor elements, such as transistors, resistors, capacitors and so on, are formed in the semiconductor substrate by using various well-known processes. Then, a multi-layered wiring structure is constructed over the semiconductor substrate.
In particular, first, an insulating layer such as a silicon dioxide layer, which defines a part of the multi-layered wiring structure, is formed on the semiconductor substrate by using a suitable chemical vapor deposition (CVD) process, and a plurality of via holes are formed in the insulating layer to obtain electrical contacts with the various semiconductor elements. Then, a suitable metal material such as a tungsten material is deposited on the silicon dioxide layer by using a sputtering process, to thereby form a tungsten layer on the insulating layer so that the via holes are completely stuffed with the tungsten material.
Next, the tungsten layer is polished by using a chemical mechanical polishing process (CMP) so as to be removed from the top surface of the insulating layer, and thus the tungsten materials, with which the via holes are stuffed, remain as tungsten via plugs electrically connected to the semiconductor elements which are formed in the substrate. Then, a suitable metal material such as an aluminum material is deposited on the top surface of the insulating layer by using a sputtering process, to thereby form an aluminum layer on the insulating layer so as to be in electrical contact with the tungsten via plugs.
Next, a photoresist layer is coated on the aluminum layer by using a spin-coat process, and then the semiconductor device (wafer) is transferred to a stepper including an alignment mark detection apparatus and an optical exposure apparatus. First, the semiconductor device (wafer) is set in the alignment mark detection apparatus, and an alignment mark element, which is previously formed on the semiconductor substrate, is optically detected, and a position of the detected alignment mark element is calculated as positional data with respect to a suitable coordinate system defined on the semiconductor substrate.
Next, the semiconductor device (wafer) is set in the optical exposure apparatus, which includes an optical projector unit having a photomask or reticle for generating a wiring pattern image, and a movable stage associated with the optical projector unit. In the optical exposure apparatus, the semiconductor device (wafer) is placed on the movable stage, and is positioned with respect to the optical projector unit based on the positional data obtained by the alignment mark detection apparatus. Then, an exposure process is carried out such that the wiring pattern image is optically projected on the photoresist layer on the photoresist semiconductor device (wafer) with an ultraviolet ray, by using the photomask or reticle.
After the exposure process is completed, the exposed photoresist layer is subjected to a developing process in which the photoresist layer is defined as a photoresist mask for transfer the wiring pattern image to the aluminum layer on the semiconductor substrate. At this time, although the photoresist mask should be precisely positioned with respect to an arrangement of the tungsten via plugs due to the aforesaid positional data of the alignment mark element, in reality, a discrepancy may be produced between the wiring pattern image and the arrangement of the tungsten via plugs.
Accordingly, after the developing process is completed, the discrepancy between the wiring pattern image and the arrangement of the tungsten via plugs is optically detected, and it is evaluated whether the discrepancy falls within a permissible range. To this end, an overlay mark including a lower mark element and an upper mark element is utilized, as disclosed in, for example, JP-2003-031484-A.
In particular, the lower mark element is defined as a groove formed in the insulating layer, and the groove usually has a square frame configuration when viewed from a location above the top surface of the insulating layer. The formation of the lower mark element in the insulating layer is simultaneously carried out when the tungsten via plugs are formed in the insulating layer, and thus the inner wall faces of the lower mark element are covered with the tungsten layer.
On the other hand, the upper mark element is defined as a square opening formed in the photoresist layer at an area encompassed by the lower mark element. The formation of the upper mark element in the photoresist layer is carried out by the exposure and developing processes. That is, the photomask or reticle has an image corresponding to the upper mark element.
The discrepancy is evaluated as a difference between the center of the lower mark element and the upper mark element.